) Multiplier Using Combinational Gates

This paper proposes the design and implementation of GF (2) multiplier using composite field arithmetic. We have introduced an irreducible polynomial X+X+ξ. This irreducible polynomial is required for transforming Galois field of GF (2) to composite field of GF (((2))). Our estimation of the value of ξ and subsequently the composite field arithmetic hence forth derived achieved high speed GF (2) multiplier. The design being purely combinational is a clock free design. We achieved critical path delay of 11.5ns between inputs to output data path. We have used combination of ᴪ and λ as {10}2 and {1100}2 respectively. Due to this value of ᴪ, λ, ξ we achieved fastest implementation, at the cost of few extra gates. The design methodology includes implementation and verification on FPGA using Xilinx ISE and finally the physical layout was designed on ASIC using 90nm CMOS standard cell libraries. Our implementation result shows that without pipelining the hardware core can achieve throughput of 5.39 Mbps on FPGA and we achieved throughput of 5.43Gbps on 90nm ASIC. Keywords— Galois field, composite field arithmetic, isomorphic mapping.